uvmforbeginners

  How can we add new functionality to our testbench ? A Key UVM guideline is to write our testbench once Basic functionality description which has a good transcations Extend the classes to add new functionality Need to make sure it won't break the existing setup UVM Factory Creates objects in the UVM Testbench Allows the new written tests to "override" the original defined object  Factory overrides are Very Important Factory overrides make it possible to write many complex scenarios to run on the same testbench Each test can customize the testbench at run time for the speicific needs of that test.

Once we have all the Verification Environment available we need to perform compile, optimize, debug and simulate the defined test to check for transcation on DUT. Below example illustrates how we can integrate our verification package with Testbench having DUT in picture. e.g  module top();  import  uvm_pkg ::*;  import tx_pkg ::*;  // create handle for Virtual interface  // instiate the DUT      initial begin  // configure Virtual interface using uvm_config_db with set() method          run_test();       end endmodule         \

When we need to group our VE (Verification Environment) files for easier compilation we need to package them as because Our  compile strategy is project specific Below example demonstrate how we can create our own package and place all the files package   tx_pkg;       import   uvm_pkg ::*;      `include "uvm_macros.svh"         `include  "tx_item.svh"        `include  "tx_sequence.svh"        `include  "tx_sequencer.svh"        `include  "tx_driver.svh"        `include  "tx_monitor.svh"        `include  "tx_agent.svh"        `include  "tx_env.svh"        `include  "tx_test.svh" endpackage : tx_pkg *** Here  uvm_pkg and uvm_macros.svh  are the predefined UVM Package and macro libraries  *** As our VE (Verification Environment) are built on these macros we need to import before  importing our own files.

In UVM, how does a test connect with environment and create stimulus? Here comes the answer create a test derived from "uvm_test" e.g class tx_test  extends  uvm_test ;       `uvm_component_utils (tx_test)         function new (string  name, uvm_component parent);          super.new(name,parent);       endfunction       tx_env        env;         // define env handle       virtual function void build_phase (uvm_phase phase);         env  = tx_env :: type_id :: create("env", this);       endfunction     virtual task  run_phase (uvm_phase  phase);          tx_sequence  seq ; // define the sequence handle          seq  =  tx_sequence :: type_id :: create ("seq", this);          phase.raise_objection (this);           seq.start(env.sqr.start);          phase.drop_objection(this);      endtask endclass       

Once all the Verification components are available we need mechanism to put all together in one box. To achieve the same we define an environment derived from  "uvm_env"   e.g class tx_env  extends uvm_env ;   `uvm_component_utils(tx_env)    function new (string name, uvm_component parent);      super.new (name,parent);     endfunction    // create the handle for agent        tx_agent           agt;    // build the handle using factory mechanism       virtual function void  build_phase (uvm_phase phase);           agt  = tx_agent :: type_id :: create ("agt", this);       endfunction endclass        

  Agent is defined to make sure all the active and passive component elements are bundled in one group. which means the components like sequencer,driver are part of active elements and monitor, scoreboard, functional coverage are part of passive elements. Need to Bundle them together in an agent defined using "uvm_agent" library e.g class  tx_agent extends  uvm_agent ;        `uvm_component_utils (tx_agent)      function new (string name = "tx_agent", uvm_component parent);            super.new (name, parent);    endfunction   //  define the handle for driver, monitor and sequencer          tx_driver          drv;          tx_monitor         mon;          tx_sequencer       sqr;  //  build driver, monitor and sequencer  using factory  definition         virtual function void  build_phase (uvm_phase phase);           drv  =  tx_driver :: type_id :: create ("drv", this);           sqr  =  tx_sequencer :: type_id :: create("sqr", this);           m

  Sequencer  are defined using  "uvm_sequencer"  library which will basically collect the item from sequence and transport it to driver using TLM mechansim. Below shows an example of defining your own sequencer class  tx_sequencer  extends  uvm_sequencer ;  `uvm_component_utils (tx_sequencer)   function new (string name = "tx_sequencer",  uvm_component parent);     super.new(name, parent);   endfunction endclass

In order to generate stimulus we need to define sequence using UVM library "uvm_sequence" and is pointed to the earlier defined sequence item. Sequences can be multiple but will be connected to sequencer before it is transferred to Driver. Let us look into one simple example wich demonstrate the definition of sequence class tx_sequence  extends uvm_sequence #(tx_item);        `uvm_object_utils(tx_sequence)        function new (string name = "tx_sequence");            super.new(name);         endfunction   // Now, define the task to generate the stimulus multiple times         virtual task body();           repeat (5)  begin   // Iterate generation for 5 times              tx_item       tx;  // handle definition for tx_item               // create tx_item handle using factory mechanism               tx  = tx_item::type_id::create("tx");                     start_item(tx);                  if (!tx.randomize() )                    `uvm_fatal(.......);      

  UVM has a built in library "uvm_driver"  used to define the  Driver component // driver points to the item as tx_item defined using sequence item class  tx_driver  extends  uvm_driver #(tx_item);   // UVM component macro registers this with the factory definition         `uvm_component_utils(tx_driver)              function new (string name, uvm_component parent);             super.new(new,parent);           endfunction           virtual task run_phase(uvm_phase  phase);             tx_item    tx;   // pointing to sequence item definition             forever begin                  seq_item_port.get_next_item(tx);                 drive_to_dut(tx);                  seq_item_port.item_done();               end            endtask            virtual  task drive_to_dut (tx_item tr);              `uvm_info("TRANSFER", $sformatf("tr.data = %4d", tr.data), UVM_LOW);            endtask endclass **** UVM_LOW   points to Message logger with verbosity level LOW **

 Following are the Various Components required to build an efficient Verification environment using UVM libraries. sequence item definition sequence  definition driver    definition agent     definition env       definition base test definition sequence library definition

  An Simple Transation can be defined using the in-built  UVM library  "uvm_sequence_item" e.g         class  tx_item extends uvm_sequence_item ;              // uvm objet macro registers this class with UVM factory                   `uvm_object_utils(tx_item)                 // constructor identifies the object                      function new (string name ="tx_item");                         super.new(name);                    endfunction              // Define variables                    rand bit [7:0]  data;           endclass                          

 UVM Components run synchrounously through UVM Phasing lke as below Build Connect End of elaboration Start of Simulation (run phase are divided into sub-domain) reset configure main shutdown extract  check report final *** All the construction phases execute in zero time and at simulation time zero *** The task() phase is where the test is run and where simulation time is consumed

UVM (Universal Verification Methodology) is open source code that provides A Methodology aimed at Reusability and Scalibility Maintability A Base class library Base definition for defining testbench verification components (sequencers, drivers, scoreboards....) A Factory Constructs objects and substitutes an objects within the testbench A Configuration Mechanism A shared hierarchical mechanism database for storing and retriving information when needed A Reporting Mechanism A consistent way of printing and logging results Transcation Level Modeling (TLM) Communication between Verification components