How to define Driver Component and drive transcation using UVM

 UVM has a built in library "uvm_driver"  used to define the  Driver component

// driver points to the item as tx_item defined using sequence item

class  tx_driver  extends  uvm_driver #(tx_item);  

// UVM component macro registers this with the factory definition

        `uvm_component_utils(tx_driver)   

         function new (string name, uvm_component parent);

            super.new(new,parent);

          endfunction

          virtual task run_phase(uvm_phase  phase);

            tx_item    tx;   // pointing to sequence item definition

            forever begin

                seq_item_port.get_next_item(tx);

                drive_to_dut(tx);

                seq_item_port.item_done();

              end

           endtask

           virtual  task drive_to_dut (tx_item tr);

            `uvm_info("TRANSFER", $sformatf("tr.data = %4d", tr.data), UVM_LOW);

           endtask

endclass

**** UVM_LOW  points to Message logger with verbosity level LOW

**** component definition have the  string and parent definition

**** For object definition have only string definition



  

 

Comments

Post a Comment

Popular posts from this blog

How to define Packages using UVM

When we need to group our VE (Verification Environment) files for easier compilation we need to package them as because Our  compile strategy is project specific Below example demonstrate how we can create our own package and place all the files package   tx_pkg;       import   uvm_pkg ::*;      `include "uvm_macros.svh"         `include  "tx_item.svh"        `include  "tx_sequence.svh"        `include  "tx_sequencer.svh"        `include  "tx_driver.svh"        `include  "tx_monitor.svh"        `include  "tx_agent.svh"        `include  "tx_env.svh"        `include  "tx_test.svh" endpackage : tx_pkg *** Here  uvm_pkg and uvm_macros.svh  are the predefined UVM Package and macro libraries  *** As our VE (Verification ...
Read more

Writing the first test class in UVM

In UVM, how does a test connect with environment and create stimulus? Here comes the answer create a test derived from "uvm_test" e.g class tx_test  extends  uvm_test ;       `uvm_component_utils (tx_test)         function new (string  name, uvm_component parent);          super.new(name,parent);       endfunction       tx_env        env;         // define env handle       virtual function void build_phase (uvm_phase phase);         env  = tx_env :: type_id :: create("env", this);       endfunction     virtual task  run_phase (uvm_phase  phase);          tx_sequence  seq ; // define the sequence handle          seq  =  tx_sequence :: type_id :: create ("seq", this);          ph...
Read more

How to Run the test using UVM

Once we have all the Verification Environment available we need to perform compile, optimize, debug and simulate the defined test to check for transcation on DUT. Below example illustrates how we can integrate our verification package with Testbench having DUT in picture. e.g  module top();  import  uvm_pkg ::*;  import tx_pkg ::*;  // create handle for Virtual interface  // instiate the DUT      initial begin  // configure Virtual interface using uvm_config_db with set() method          run_test();       end endmodule         \
Read more