How to define an Testbench Environment in UVM methodology

Once all the Verification components are available we need mechanism to put all together in one box.

To achieve the same we define an environment derived from  "uvm_env" 

e.g

class tx_env  extends uvm_env;

  `uvm_component_utils(tx_env)

   function new (string name, uvm_component parent);

     super.new (name,parent);

    endfunction

   // create the handle for agent

       tx_agent           agt;

   // build the handle using factory mechanism

      virtual function void  build_phase (uvm_phase phase);

          agt  = tx_agent :: type_id :: create ("agt", this);

      endfunction

endclass