uvmforbeginners

Once we have all the Verification Environment available we need to perform compile, optimize, debug and simulate the defined test to check for transcation on DUT. Below example illustrates how we can integrate our verification package with Testbench having DUT in picture. e.g  module top();  import  uvm_pkg ::*;  import tx_pkg ::*;  // create handle for Virtual interface  // instiate the DUT      initial begin  // configure Virtual interface using uvm_config_db with set() method          run_test();       end endmodule         \

When we need to group our VE (Verification Environment) files for easier compilation we need to package them as because Our  compile strategy is project specific Below example demonstrate how we can create our own package and place all the files package   tx_pkg;       import   uvm_pkg ::*;      `include "uvm_macros.svh"         `include  "tx_item.svh"        `include  "tx_sequence.svh"        `include  "tx_sequencer.svh"        `include  "tx_driver.svh"        `include  "tx_monitor.svh"        `include  "tx_agent.svh"        `include  "tx_env.svh"        `include  "tx_test.svh" endpackage : tx_pkg *** Here  uvm_pkg and uvm_macros.svh  are the predefined UVM Package and macro libraries  *** As our VE (Verification Environment) are built on these macros we need to import before  importing our own files.

In UVM, how does a test connect with environment and create stimulus? Here comes the answer create a test derived from "uvm_test" e.g class tx_test  extends  uvm_test ;       `uvm_component_utils (tx_test)         function new (string  name, uvm_component parent);          super.new(name,parent);       endfunction       tx_env        env;         // define env handle       virtual function void build_phase (uvm_phase phase);         env  = tx_env :: type_id :: create("env", this);       endfunction     virtual task  run_phase (uvm_phase  phase);          tx_sequence  seq ; // define the sequence handle          seq  =  tx_sequence :: type_id :: create ("seq", this);          phase.raise_objection (this);           seq.start(env.sqr.start);          phase.drop_objection(this);      endtask endclass       

Once all the Verification components are available we need mechanism to put all together in one box. To achieve the same we define an environment derived from  "uvm_env"   e.g class tx_env  extends uvm_env ;   `uvm_component_utils(tx_env)    function new (string name, uvm_component parent);      super.new (name,parent);     endfunction    // create the handle for agent        tx_agent           agt;    // build the handle using factory mechanism       virtual function void  build_phase (uvm_phase phase);           agt  = tx_agent :: type_id :: create ("agt", this);       endfunction endclass        

  Agent is defined to make sure all the active and passive component elements are bundled in one group. which means the components like sequencer,driver are part of active elements and monitor, scoreboard, functional coverage are part of passive elements. Need to Bundle them together in an agent defined using "uvm_agent" library e.g class  tx_agent extends  uvm_agent ;        `uvm_component_utils (tx_agent)      function new (string name = "tx_agent", uvm_component parent);            super.new (name, parent);    endfunction   //  define the handle for driver, monitor and sequencer          tx_driver          drv;          tx_monitor         mon;          tx_sequencer       sqr;  //  build driver, monitor and sequencer  using factory  definition         virtual function void  build_phase (uvm_phase phase);           drv  =  tx_driver :: type_id :: create ("drv", this);           sqr  =  tx_sequencer :: type_id :: create("sqr", this);           m

  Sequencer  are defined using  "uvm_sequencer"  library which will basically collect the item from sequence and transport it to driver using TLM mechansim. Below shows an example of defining your own sequencer class  tx_sequencer  extends  uvm_sequencer ;  `uvm_component_utils (tx_sequencer)   function new (string name = "tx_sequencer",  uvm_component parent);     super.new(name, parent);   endfunction endclass